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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-24 22:35:29 +0200 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-08-30 18:59:23 +0200 |
| commit | 309fc4ce8bad334b88fc653a35baa4f0c5b67fd2 (patch) | |
| tree | 9e7fe586c290f9b3bff31039e19c2e112a2e3d07 /src/northbridge/intel | |
| parent | 3a2310e05c971e3b46e9e91886bbc467ae49cdb6 (diff) | |
| download | coreboot-309fc4ce8bad334b88fc653a35baa4f0c5b67fd2.tar.xz | |
sandybridge: Add native sandybridge
Change-Id: I1b51310b4387e588c4828563620b0e2770598503
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6753
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 16 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 3 |
3 files changed, 17 insertions, 3 deletions
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc index 4fb91e8964..ffda444281 100644 --- a/src/northbridge/intel/Makefile.inc +++ b/src/northbridge/intel/Makefile.inc @@ -14,6 +14,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += nehalem subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += sandybridge subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 79767213f8..18fd175bfc 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -25,6 +25,14 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX +config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE + bool + select CACHE_MRC_BIN + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select CPU_INTEL_MODEL_206AX + select HAVE_DEBUG_RAM_SETUP + config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN @@ -41,7 +49,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP -if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE +if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE config VGA_BIOS_ID string @@ -66,8 +74,10 @@ config MRC_CACHE_SIZE config DCACHE_RAM_BASE hex - default 0xff7e0000 if !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + default 0xff7e0000 if NORTHBRIDGE_INTEL_IVYBRIDGE + default 0xff7e0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE default 0xfefe0000 if NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + default 0xfefe0000 if NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE config DCACHE_RAM_SIZE hex @@ -83,7 +93,7 @@ config DCACHE_RAM_MRC_VAR_SIZE config HAVE_MRC bool "Add a System Agent binary" - depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + depends on !NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE && !NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE help Select this option to add a System Agent binary to the resulting coreboot image. diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index de31288cf7..5dfd87788d 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -31,6 +31,8 @@ romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += raminit.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += raminit.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += raminit_native.c romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += raminit_native.c +romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += ../../../device/dram/ddr3.c romstage-y += mrccache.c romstage-y += early_init.c romstage-y += report_platform.c @@ -56,6 +58,7 @@ mrc.cache-file := $(obj)/mrc.cache mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) := 0xfffd0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) := 0xfffd0000 mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) := 0xfffe0000 +mrc-cache-position-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) := 0xfffe0000 mrc.cache-position := $(mrc-cache-position-y) mrc.cache-type := 0xac endif |