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authorKeith Hui <buurin@gmail.com>2020-04-16 20:45:30 -0400
committerPatrick Georgi <pgeorgi@google.com>2020-05-04 09:39:14 +0000
commit67c73110e96ec6f1ec90c12f1ed6aac95107e896 (patch)
tree87df8ae0c921d136466bc014200e33c44b021e4b /src/northbridge/intel
parent336d9a214843c4312eea9f00f2ce7c74ca87500b (diff)
downloadcoreboot-67c73110e96ec6f1ec90c12f1ed6aac95107e896.tar.xz
nb/intel/i440bx: Resolve a SMP-raminit TODO
Change-Id: I0087294bccee079368c93ba8986873a5e65593b0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i440bx/raminit.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index dddcc217f4..ee1e75902e 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -123,8 +123,11 @@ static const u8 register_values[] = {
* [01:00] Reserved
*/
NBXCFG + 0, 0x0c,
- // TODO: Bit 15 should be 0 for multiprocessor boards
+#if CONFIG(SMP)
+ NBXCFG + 1, 0x00,
+#else
NBXCFG + 1, 0x80,
+#endif
NBXCFG + 2, 0x00,
NBXCFG + 3, 0xff,