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authorRonald G. Minnich <rminnich@gmail.com>2004-11-11 14:04:25 +0000
committerRonald G. Minnich <rminnich@gmail.com>2004-11-11 14:04:25 +0000
commit8d41ad83befa12b905bdde5fb853898c3569f0e9 (patch)
tree2400e2d1093cdae54c4fa51f427eb451367ac2bf /src/northbridge/intel
parent029517c77a1d756ccbb196b5178ba2a1cf952c97 (diff)
downloadcoreboot-8d41ad83befa12b905bdde5fb853898c3569f0e9.tar.xz
in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it.
Set adl855pc ROM_SIZE to 1M Other minor debug prints until we get this fixed. We're almost as far along as we were before the Change :-) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i855pm/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i855pm/raminit.c b/src/northbridge/intel/i855pm/raminit.c
index 5066f424bf..64266d26e6 100644
--- a/src/northbridge/intel/i855pm/raminit.c
+++ b/src/northbridge/intel/i855pm/raminit.c
@@ -17,9 +17,9 @@
/* converted to C 6/2004 yhlu */
-#define DEBUG_RAM_CONFIG 1
+#define DEBUG_RAM_CONFIG 12
#undef ASM_CONSOLE_LOGLEVEL
-#define ASM_CONSOLE_LOGLEVEL 9
+#define ASM_CONSOLE_LOGLEVEL 10
#define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1))
/* DDR DIMM Mode register Definitions */