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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-09 21:23:25 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-11 09:05:40 +0000 |
| commit | 96184e9f2d911bb8346b90bb2052b7da090b533b (patch) | |
| tree | 669ae957fb5b586a37dd0ae7ebe09148955f8c6c /src/northbridge/intel | |
| parent | 322fa32e5e4b396ffba3f12cdb128b3aa4624f3c (diff) | |
| download | coreboot-96184e9f2d911bb8346b90bb2052b7da090b533b.tar.xz | |
nb/intel/i945/bootblock.c: Correct comment
Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i945/bootblock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 4c3c90c49b..1b70df57d3 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -9,8 +9,8 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to - * to true. That way all subsequent non-explicit config accesses use + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to true. + * That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the |