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| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2013-05-08 17:08:55 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-07-02 21:07:44 +0200 |
| commit | abe6847cd21b553dd66fcb0540de166f82ebaf00 (patch) | |
| tree | 76802c070016f3e84dc29d7c2d321014700eca88 /src/northbridge/intel | |
| parent | 59158b2fb0eda826feaa7ae99d5fe2a284c569d3 (diff) | |
| download | coreboot-abe6847cd21b553dd66fcb0540de166f82ebaf00.tar.xz | |
Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c`
Use the same indentation, comment placement and spelling of words.
Run `indent -linux …`.
Change-Id: Id5765c45b28058cdd50ee4c0a1fd9f645ad7f3f8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3220
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/delay.c | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/udelay.c | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/udelay.c | 4 |
3 files changed, 6 insertions, 8 deletions
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c index a861e250c2..0b5ecd99b4 100644 --- a/src/northbridge/intel/gm45/delay.c +++ b/src/northbridge/intel/gm45/delay.c @@ -24,7 +24,7 @@ #include "delay.h" /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ static void _udelay(const u32 us, const u32 numerator, const int total) { @@ -62,8 +62,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - /* CPU clock is always a quarter. */ - d = ((fsb * divisor) / numerator) / 4; + d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c index 3d5d6c6d9c..60ca9fb61a 100644 --- a/src/northbridge/intel/i945/udelay.c +++ b/src/northbridge/intel/i945/udelay.c @@ -24,7 +24,7 @@ #include <cpu/intel/speedstep.h> /** - * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock + * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock */ void udelay(u32 us) @@ -63,7 +63,7 @@ void udelay(u32 us) msr = rdmsr(0x198); divisor = (msr.hi >> 8) & 0x1f; - d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ + d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */ multiply_to_tsc(&tscd, us, d); @@ -79,5 +79,4 @@ void udelay(u32 us) tsc = rdtsc(); } while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); - } diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c index 449b0b99a8..608726c95b 100644 --- a/src/northbridge/intel/sandybridge/udelay.c +++ b/src/northbridge/intel/sandybridge/udelay.c @@ -23,7 +23,7 @@ #include <cpu/x86/msr.h> /** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz */ void udelay(u32 us) @@ -37,7 +37,7 @@ void udelay(u32 us) msr = rdmsr(0xce); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc(); |