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authorArthur Heymans <arthur@aheymans.xyz>2018-04-10 12:57:42 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-12-03 10:18:14 +0000
commitcf3076eff17dc9c152fca6ec9012e7734ff88b4c (patch)
treeca4fd543bd87f02b3ff0e001ceca30c9c94c2f03 /src/northbridge/intel
parent6af3e6f4ff2ff727fec3034ef64c6dd604d44c9c (diff)
downloadcoreboot-cf3076eff17dc9c152fca6ec9012e7734ff88b4c.tar.xz
nb/intel/i945: Use common SMM_TSEG code
Use the common SMM_TSEG code to relocate the smihandler to TSEG. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. This fixes S3 resume being broken introduced by CB:25594 "sb/intel/i82801gx: Use common Intel SMM code". Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel d945gclf and Lenovo Thinkpad X60. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25595 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i945/Kconfig1
-rw-r--r--src/northbridge/intel/i945/northbridge.c31
-rw-r--r--src/northbridge/intel/i945/ram_calc.c26
3 files changed, 49 insertions, 9 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 549f4dfd59..92bf65279d 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select POSTCAR_STAGE
select POSTCAR_CONSOLE
+ select SMM_TSEG
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index bec0c58d9b..ef3c59cb72 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -24,6 +24,7 @@
#include <string.h>
#include <cpu/cpu.h>
#include <arch/acpi.h>
+#include <cpu/intel/smm/gen1/smi.h>
#include "i945.h"
static int get_pcie_bar(u32 *base)
@@ -154,6 +155,36 @@ static const char *northbridge_acpi_name(const struct device *dev)
return NULL;
}
+void northbridge_write_smram(u8 smram)
+{
+ struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+
+ if (dev == NULL)
+ die("could not find pci 00:00.0!\n");
+
+ pci_write_config8(dev, SMRAM, smram);
+}
+
+/*
+ * Really doesn't belong here but will go away with parallel mp init,
+ * so let it be here for a while...
+ */
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+ unsigned int i;
+
+ /* Logical processors (threads) per core */
+ const struct cpuid_result cpuid1 = cpuid(1);
+ /* Read number of cores. */
+ const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+ /* TODO in parallel MP cpuid(1).ebx */
+ for (i = 0; i < cores; i++)
+ apic_id_map[i] = i;
+
+ return cores;
+}
+
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 7ee71985cd..fd37aea08c 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -24,6 +24,7 @@
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>
+#include <cpu/intel/smm/gen1/smi.h>
/* Decodes TSEG region size to bytes. */
u32 decode_tseg_size(const u8 esmramc)
@@ -43,7 +44,7 @@ u32 decode_tseg_size(const u8 esmramc)
}
}
-static uintptr_t smm_region_start(void)
+u32 northbridge_get_tseg_base(void)
{
uintptr_t tom;
@@ -58,13 +59,20 @@ static uintptr_t smm_region_start(void)
return tom;
}
-/* Depending of UMA and TSEG configuration, TSEG might start at any
+u32 northbridge_get_tseg_size(void)
+{
+ const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
+ return decode_tseg_size(esmramc);
+}
+
+/*
+ * Depending of UMA and TSEG configuration, TSEG might start at any
* 1 MiB alignment. As this may cause very greedy MTRR setup, push
* CBMEM top downwards to 4 MiB boundary.
*/
void *cbmem_top(void)
{
- uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB);
+ uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
return (void *) top_of_ram;
}
@@ -99,14 +107,14 @@ void platform_enter_postcar(void)
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
- /* Cache two separate 4 MiB regions below the top of ram, this
- * satisfies MTRR alignment requirements. If you modify this to
- * cover TSEG, make sure UMA region is not set with WRBACK as it
- * causes hard-to-recover boot failures.
+ /* Cache 8 MiB region below the top of ram and 2 MiB above top of
+ * ram to cover both cbmem as the TSEG region.
*/
top_of_ram = (uintptr_t)cbmem_top();
- postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
- postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
+ MTRR_TYPE_WRBACK);
+ postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
+ northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
run_postcar_phase(&pcf);