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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-04-28 18:04:35 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-04-29 15:58:34 +0000 |
| commit | d45f33804db1e4181e2f657727adc51842aa9a60 (patch) | |
| tree | dc242be28fc20b0ad27d561d62d982cce05e33de /src/northbridge/intel | |
| parent | 82d4642805bb3d5018e2580c4a7edfc6bdb9138a (diff) | |
| download | coreboot-d45f33804db1e4181e2f657727adc51842aa9a60.tar.xz | |
nb/intel/nehalem: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions.
Change-Id: Ib7e399b5186aa704d0388c4a4b18480f2e3799f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 3164a58fbf..5b6077f5ea 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -22,6 +22,7 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cbmem.h> +#include <cf9_reset.h> #include <arch/cbfs.h> #include <ip_checksum.h> #include <pc80/mc146818rtc.h> @@ -3681,8 +3682,7 @@ void chipset_init(const int s3resume) if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) { printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); MCHBAR8(0x2ca8) = 0; - outb(0x6, 0xcf9); - halt(); + system_reset(); } #if 0 if (!s3resume) { @@ -3907,8 +3907,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); - outb(0x6, 0xcf9); - halt(); + system_reset(); } } @@ -4346,8 +4345,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) "Couldn't find training data. Rebooting\n"); reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - outb(0xe, 0xcf9); - halt(); + full_reset(); } int tm; info.training = *info.cached_training; @@ -4788,7 +4786,6 @@ void raminit(const int s3resume, const u8 *spd_addrmap) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); /* Failed S3 resume, reset to come up cleanly */ - outb(0xe, 0xcf9); - halt(); + full_reset(); } } |