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authorRyan Salsamendi <rsalsamendi@hotmail.com>2017-06-30 17:36:41 -0700
committerNico Huber <nico.h@gmx.de>2017-07-03 17:15:50 +0000
commitdab81a4e2647a4ccdafcd7f5a4b40736bc3a4269 (patch)
tree22dbd5c7591e00620a4b0172db7df6447910d12a /src/northbridge/intel
parent312b23522ad8fa76bc6a79cd87e2b327635edb77 (diff)
downloadcoreboot-dab81a4e2647a4ccdafcd7f5a4b40736bc3a4269.tar.xz
northbridge/intel/haswell: Fix copy paste error
DIMMB's DDR width is in bit 20, not bit 19. Change-Id: I48866d9243c2a576a02519724429801ae47c5644 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/haswell/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index aa07f16625..e48cca9f6f 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -104,7 +104,7 @@ static void report_memory_config(void)
((ch_conf >> 16) & 1) ? "" : ", selected");
printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n",
((ch_conf >> 8) & 0xff) * 256,
- ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
+ ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
((ch_conf >> 18) & 1) ? "dual" : "single",
((ch_conf >> 16) & 1) ? ", selected" : "");
}