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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-08 19:00:54 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-06-01 11:11:26 +0200 |
| commit | ee62164bb2052b065e72c5202c221b600401e0bc (patch) | |
| tree | d542abaddfbef56da89611f1e1f545aeb4a4e838 /src/northbridge/intel | |
| parent | 25b55f3d1ceb4fdf67ffb29ed4080dfd5f4e5916 (diff) | |
| download | coreboot-ee62164bb2052b065e72c5202c221b600401e0bc.tar.xz | |
lenovo/x201: Fix order of SPI init.
The lock bit for UVSVC/LVSVC was set before both registers were programmed.
Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5167
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions