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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-12-28 21:20:45 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-01-10 19:53:24 +0100 |
| commit | 18537817484580fef1f154cb3fcb2574d3f5a858 (patch) | |
| tree | 884a4f64a4bc8becd0346f6d1b4d274ec96c2447 /src/northbridge/intel | |
| parent | 21b01b80d6a11a24d69a3e7ccd7c113681b6dcee (diff) | |
| download | coreboot-18537817484580fef1f154cb3fcb2574d3f5a858.tar.xz | |
nb/intel/945gc: Hardcode the integrated graphic frequencies
The code to set the igd frequencies is written with the mobile version
of the 945 chipset in mind and seems to cause cause strange igd
related problems on the desktop versions.
Some possible problems are:
* on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
* on 800MHz fsb CPU memtest results vary a lot;
* since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
variant board scheme" that does not affect this northbridge, the
display shows garbage as soon as Linux (4.8) modesets the display.
A fix is to hardcode the core display and render clocks to their
maximum, potentially also improving graphical performance.
Vendor bios on all boards in coreboot with this northbridge have the
same value in this PCI config address.
TESTED on P5GC-MX (display works fine again in Linux) and
user reports of it making GA-945GCM-S2L run more stable.
Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17981
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a4a1eaf0ca..f9ba37b17b 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3116,8 +3116,14 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Program PLL settings */ sdram_program_pll_settings(&sysinfo); - /* Program Graphics Frequency */ - sdram_program_graphics_frequency(&sysinfo); + /* + * Program Graphics Frequency + * Set core display and render clock on 945GC to the max + */ + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + sdram_program_graphics_frequency(&sysinfo); + else + pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); /* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo); |