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authorMyles Watson <mylesgw@gmail.com>2010-09-13 13:14:48 +0000
committerMyles Watson <mylesgw@gmail.com>2010-09-13 13:14:48 +0000
commit25d1213e3fd596281f2d7a3bb3aa975a4bf66545 (patch)
tree78c0bc88e353f58fee9c78e8043a9daf160dc02d /src/northbridge/intel
parent43882f1714a5fd415cdf3dab1dfd6328fb2f0a33 (diff)
downloadcoreboot-25d1213e3fd596281f2d7a3bb3aa975a4bf66545.tar.xz
Convert i945 boards to use reserved resources instead of directly adding
coreboot table entries in every mainboard. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i945/northbridge.c26
1 files changed, 17 insertions, 9 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 0f5a502b69..aab82bdd4a 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -70,20 +70,26 @@ static int get_pcie_bar(u32 *base, u32 *len)
/* IDG memory */
uint64_t uma_memory_base=0, uma_memory_size=0;
-int add_northbridge_resources(struct lb_memory *mem)
+static void add_fixed_resources(struct device *dev, int index)
{
+ struct resource *resource;
u32 pcie_config_base, pcie_config_size;
printk(BIOS_DEBUG, "Adding UMA memory area\n");
- lb_add_memory_range(mem, LB_MEM_RESERVED,
- uma_memory_base, uma_memory_size);
-
- printk(BIOS_DEBUG, "Adding PCIe config bar\n");
- get_pcie_bar(&pcie_config_base, &pcie_config_size);
- lb_add_memory_range(mem, LB_MEM_RESERVED,
- pcie_config_base, pcie_config_size);
+ resource = new_resource(dev, index);
+ resource->base = (resource_t) uma_memory_base;
+ resource->size = (resource_t) uma_memory_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
- return 0;
+ if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+ printk(BIOS_DEBUG, "Adding PCIe config bar\n");
+ resource = new_resource(dev, index+1);
+ resource->base = (resource_t) pcie_config_base;
+ resource->size = (resource_t) pcie_config_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ }
}
static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
@@ -208,6 +214,8 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
}
+ add_fixed_resources(dev, 6);
+
assign_resources(dev->link_list);
#if CONFIG_WRITE_HIGH_TABLES==1