summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
authorVladimir Serbinenko <phcoder@gmail.com>2016-01-29 19:42:02 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2016-01-29 20:45:09 +0100
commit3141eac9007634710d9e307170e821f805204683 (patch)
tree394b39b218237823f2108fff6db1f0da39927dc1 /src/northbridge/intel
parent1bf5e6409678d04fd15f9625460078853118521c (diff)
downloadcoreboot-3141eac9007634710d9e307170e821f805204683.tar.xz
Revert "northbridge/intel/sandybridge: Fix random raminit failures"
It break x230 access to channel 1. This reverts commit 9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238. Change-Id: I8a3b13d17729f25cea3460ac2f87bca3c193d388 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13512 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c12
1 files changed, 1 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 151a7ec4d4..8a287c184c 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -2334,17 +2334,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
}
FOR_ALL_LANES {
struct run rn = get_longest_zero_run(statistics[lane], 128);
- if (rn.start < rn.middle) {
- ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
- } else {
- /* In this case statistics[lane][7f] and statistics[lane][0] are
- * both zero.
- * Prefer a smaller value over rn.start to prevent failures in
- * the following write tests.
- */
- ctrl->timings[channel][slotrank].lanes[lane].timB = 0;
- }
-
+ ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
if (rn.all)
die("timB discovery failed");
printram("Bval: %d, %d, %d, %x\n", channel, slotrank,