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| author | Stefan Reinauer <reinauer@chromium.org> | 2014-12-17 13:23:05 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2014-12-18 02:10:03 +0100 |
| commit | 61ed48c9233e0d74ef5c6847052662d075553691 (patch) | |
| tree | 175715f83a1dca3e5ce3c391801a2150b79805cf /src/northbridge/intel | |
| parent | 1882d65364fad35485dbe2069c23059c78320e3b (diff) | |
| download | coreboot-61ed48c9233e0d74ef5c6847052662d075553691.tar.xz | |
intel/truxton: Un-romcc-ify board
Change-Id: Iaf1756321960041f6a152d5dd4c9108291f51300
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7852
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.c | 13 | ||||
| -rw-r--r-- | src/northbridge/intel/i3100/raminit_ep80579.h | 1 |
2 files changed, 4 insertions, 10 deletions
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 962b7aa86b..cff7879f5e 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -18,6 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <lib.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/intel/speedstep.h> @@ -37,7 +38,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0, }; int i; - int max; for (i = 0; i < ARRAY_SIZE(register_values); i += 3) { device_t dev; @@ -61,7 +61,7 @@ static struct dimm_size spd_get_dimm_size(u16 device) { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, ddr2; + int value, low; sz.side1 = 0; sz.side2 = 0; @@ -489,7 +489,6 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, static void sdram_set_spd_registers(const struct mem_controller *ctrl) { u8 dimm_mask; - int i; /* Test if we can read the SPD */ dimm_mask = spd_detect_dimms(ctrl); @@ -503,9 +502,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { u8 c1,c2; - u32 dimm, i; + u32 i; u32 data32 = 0; - u32 t4; /* Set up northbridge values */ /* ODT enable */ @@ -565,8 +563,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) u32 drc; u32 data32; u32 mode_reg; - msr_t msr; - u16 data16; mask = spd_detect_dimms(ctrl); print_debug("Starting SDRAM Enable\n"); @@ -771,9 +767,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* Set the ECC mode */ pci_write_config32(ctrl->f0, DRC, drc); - - /* The memory is now set up--use it */ - cache_ramstage(); } static inline int memory_initialized(void) diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h index 38c68454fc..e84736df6d 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.h +++ b/src/northbridge/intel/i3100/raminit_ep80579.h @@ -27,4 +27,5 @@ struct mem_controller { u16 channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); #endif |