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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 11:42:22 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-08 22:16:15 +0000
commite816829e7a422d588fc9ff6a11507c15e6be696c (patch)
tree80c2fba2f2bd9ce082c9bb44b51bbc8be5c8ab91 /src/northbridge/intel
parent8d3bc498760fdf98713f1d977a79268d2fb1288c (diff)
downloadcoreboot-e816829e7a422d588fc9ff6a11507c15e6be696c.tar.xz
haswell: drop unused function parameter
The `chipset_type` parameter is ignored. Change-Id: Ia3d217178cc9caabf232b3a59f505229cc03135f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/haswell/early_init.c2
-rw-r--r--src/northbridge/intel/haswell/haswell.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index fd188a1af0..9db6a9d0de 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -176,7 +176,7 @@ static void haswell_setup_iommu(void)
reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
}
-void haswell_early_initialization(int chipset_type)
+void haswell_early_initialization(void)
{
/* Setup all BARs required for early PCIe and raminit */
haswell_setup_bars();
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index bd441685b7..c3930493da 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -189,7 +189,7 @@
void intel_northbridge_haswell_finalize_smm(void);
-void haswell_early_initialization(int chipset_type);
+void haswell_early_initialization(void);
void haswell_late_initialization(void);
void set_translation_table(int start, int end, u64 base, int inc);
void haswell_unhide_peg(void);