diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-12 00:05:00 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-19 16:59:34 +0200 |
| commit | 063cd5f6eee0ad9416e62eac4a168591220f53d0 (patch) | |
| tree | 7f9196330bbae483274cfcb93b14a8f094b0e173 /src/northbridge/intel | |
| parent | f2b8d7cbd6d92adac26cbd639bb51f29b237fbc0 (diff) | |
| download | coreboot-063cd5f6eee0ad9416e62eac4a168591220f53d0.tar.xz | |
nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding it
According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express
Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the
dotclock is below 225MHz and 5 when its above 225MHz.
Change-Id: I363039b6fd92051c4be4fdc88788f27527645944
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16991
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/gma.c | 15 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/gma.c | 15 |
2 files changed, 22 insertions, 8 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 9707d2f9cc..026a165def 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -362,6 +362,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, u32 target_frequency; u32 smallest_err = 0xffffffff; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -465,13 +466,15 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, vga_textmode_init(); } + pixel_p2 = target_frequency <= 225000 ? 10 : 5; + u32 candn, candm1, candm2, candp1; for (candn = 1; candn <= 4; candn++) { for (candm1 = 23; candm1 >= 17; candm1--) { for (candm2 = 11; candm2 >= 5; candm2--) { for (candp1 = 8; candp1 >= 1; candp1--) { u32 m = 5 * (candm1 + 2) + (candm2 + 2); - u32 p = candp1 * 10; /* 10 == p2 */ + u32 p = candp1 * pixel_p2; u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); u32 dot = DIV_ROUND_CLOSEST(vco, p); u32 this_err = ABS(dot - target_frequency); @@ -516,23 +519,27 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, link_frequency); printk(BIOS_SPEW, "Link M1=%d, N1=%d\n", link_m1, link_n1); - printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * 10))); + (pixel_n + 2) / (pixel_p1 * pixel_p2))); mdelay(1); write32(mmio + FP0(0), (pixel_n << 16) | (pixel_m1 << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) | (0x10000 << (pixel_p1 - 1)) | (6 << 9)); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) | (0x10000 << (pixel_p1 - 1)) | (6 << 9)); diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index e950386d3c..eb419c9f7d 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -70,6 +70,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, u32 err_most = 0xffffffff; u32 pixel_p1 = 1; + u32 pixel_p2; u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; @@ -178,13 +179,15 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, vga_textmode_init(); } + pixel_p2 = target_frequency <= 225000 ? 10 : 5; + u32 candn, candm1, candm2, candp1; for (candn = 1; candn <= 4; candn++) { for (candm1 = 23; candm1 >= 16; candm1--) { for (candm2 = 11; candm2 >= 5; candm2--) { for (candp1 = 8; candp1 >= 1; candp1--) { u32 m = 5 * (candm1 + 2) + (candm2 + 2); - u32 p = candp1 * 10; /* 10 == p2 */ + u32 p = candp1 * pixel_p2; u32 vco = DIV_ROUND_CLOSEST( BASE_FREQUENCY * m, candn + 2); u32 dot = DIV_ROUND_CLOSEST(vco, p); @@ -230,23 +233,27 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, link_frequency); printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", link_m1, link_n1); - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / - (pixel_n + 2) / (pixel_p1 * 10)); + (pixel_n + 2) / (pixel_p1 * pixel_p2)); mdelay(1); write32(mmio + FP0(0), (pixel_n << 16) | (pixel_m1 << 8) | pixel_m2); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) | (0x10000 << (pixel_p1 - 1)) | (6 << 9)); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (pixel_p2 == 10 ? DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 : + DPLL_DAC_SERIAL_P2_CLOCK_DIV_5) | (0x10000 << (pixel_p1 - 1)) | (6 << 9)); |