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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-20 20:25:21 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-08-24 07:37:12 +0200 |
| commit | 3f9a62e5ade9bf2461c93ac8c6b52c4bdca09742 (patch) | |
| tree | 859468a77adae5afb44287b59c13a5fcdbfca372 /src/northbridge/intel | |
| parent | a2adaeb68cdecc2bc1185613a11b7d49915883ec (diff) | |
| download | coreboot-3f9a62e5ade9bf2461c93ac8c6b52c4bdca09742.tar.xz | |
Add pci_devfn_t and use with __SIMPLE_DEVICE__
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PCI access
functions for ramstage using the inlined functions from romstage.
Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/gm45/ram_calc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 4590544765..28e947b393 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -85,7 +85,7 @@ u32 decode_igd_gtt_size(const u32 gsm) u32 get_top_of_ram(void) { - const device_t dev = PCI_DEV(0, 0, 0); + const pci_devfn_t dev = PCI_DEV(0, 0, 0); u32 tor; |