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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-05-09 17:19:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-13 09:27:21 +0000 |
| commit | 44105942df5a396c5ff999d7dd8384bfd44784c0 (patch) | |
| tree | 657e73717db8533e79e3d3ca0753f0b8624c315a /src/northbridge/intel | |
| parent | 60ab1d8c52799d70d1956ce7261d94be439aa63a (diff) | |
| download | coreboot-44105942df5a396c5ff999d7dd8384bfd44784c0.tar.xz | |
nb/intel/sandybridge: Update pei_data comments
Update outdated comments.
Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/pei_data.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 0a60707136..8e98becbe3 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -105,9 +105,10 @@ struct pei_data uint16_t usb_port_config[16][3]; /* See the usb3 struct above for details */ pch_usb3_controller_settings usb3; - /* SPD data array for onboard RAM. Specify address 0xf0, - * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in - * spd_address for a given "DIMM". + /* SPD data array for onboard RAM. + * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled" + * flag and the spd_addresses are used to determine which DIMMs should + * use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; |