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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-17 10:00:28 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-22 10:50:51 +0200 |
| commit | 75d139bdf28077c46b144f8380bb275fddb1bb6b (patch) | |
| tree | 812fd5b40f90a2aabfd47036bea8c210b0aef2e8 /src/northbridge/intel | |
| parent | 8431fcb8c8e248d777723e0a6651b9030d29cf8e (diff) | |
| download | coreboot-75d139bdf28077c46b144f8380bb275fddb1bb6b.tar.xz | |
intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15231
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index df0c5bbba5..a2ca1c1835 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -43,7 +43,10 @@ static void early_pch_init(void) pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); } -void main(unsigned long bist) +/* Platform has no romstage entry point under mainboard directory, + * so this one is named with prefix mainboard. + */ +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; |