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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-01 11:21:53 +0300 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-07-04 03:10:22 +0200 |
| commit | 9e974232e4896ee971745c5127cbc37f1682171b (patch) | |
| tree | adacdfe76da0f950c518db7f81af96ba98a8c02a /src/northbridge/intel | |
| parent | 575e6817e690d1540bfa14a0b1fc7b8a40ef095a (diff) | |
| download | coreboot-9e974232e4896ee971745c5127cbc37f1682171b.tar.xz | |
intel/i5000: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on two boards
with i5000 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: I26f1c2da5ae98aeeda78bdcae0fb1e8c711a3586
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i5000/Kconfig | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/i5000/bootblock.c | 21 |
2 files changed, 30 insertions, 1 deletions
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index b9c3547770..f7344ca97d 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -20,9 +20,17 @@ config NORTHBRIDGE_INTEL_I5000 bool select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP +if NORTHBRIDGE_INTEL_I5000 + config NORTHBRIDGE_INTEL_I5000_RAM_CHECK bool prompt "Run ramcheck after RAM initialization" - depends on NORTHBRIDGE_INTEL_I5000 + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/i5000/bootblock.c" + +endif diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c new file mode 100644 index 0000000000..eabbee6d63 --- /dev/null +++ b/src/northbridge/intel/i5000/bootblock.c @@ -0,0 +1,21 @@ +#include <arch/io.h> + +static void bootblock_northbridge_init(void) +{ + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + + /* setup PCIe MMCONF base address */ + pci_io_write_config32(PCI_DEV(0, 16, 0), 0x64, + CONFIG_MMCONF_BASE_ADDRESS >> 16); +} |