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| author | Furquan Shaikh <furquan@google.com> | 2019-07-06 23:05:23 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-07 07:53:33 +0000 |
| commit | b29da7f79e7cfb16f5d8b23057bd91df760f79d3 (patch) | |
| tree | bae25799dc40792c06487f534dcc5c57061c0513 /src/northbridge/intel | |
| parent | 451ef598e6d4caff5cb8d9d798bfbb2b6874f627 (diff) | |
| download | coreboot-b29da7f79e7cfb16f5d8b23057bd91df760f79d3.tar.xz | |
soc/intel/{cannonlake,icelake}: Do not define PCH_DEV_PMC in ramstage
This change intentionally removes the definition of PCH_DEV_PMC from
ramstage to avoid silent errors. This device gets hidden from PCI bus
in FSP-S and hence dropped from the root bus by the resource
allocator. In order to avoid incorrect references to the device, avoid
defining it in ramstage where it known to return NULL.
BUG=b:136861224
Change-Id: I4f69470ec80c7127a2b604ed2b1f794f5a63e126
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34120
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions