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authorPatrick Rudolph <siro@das-labor.org>2017-08-08 13:13:51 +0200
committerMartin Roth <martinroth@google.com>2017-08-10 16:09:01 +0000
commitb794a69ce9b2cbb9d6565cf0f3ac609402ad680a (patch)
treef200de26860f1d7f1465bb604f29e08b29f6cbc1 /src/northbridge/intel
parentdb27e3384a596aad4e33abf535a72d42f7aab1e8 (diff)
downloadcoreboot-b794a69ce9b2cbb9d6565cf0f3ac609402ad680a.tar.xz
nb/intel/sandybridge/raminit: Add Kconfig option for fuses
Add a new Kconfig option to ignore memory fuses that limit the maximum DRAM frequency to be used. The option is disabled by default and should only enabled by experienced users as it might decrease system stability or prevent a successful RAM training. Remove conflicting devicetree settings. Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nicola Corna <nicola@corna.info>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig12
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c3
2 files changed, 15 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 2d13f286e9..7c954fbbcb 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -44,6 +44,18 @@ config USE_NATIVE_RAMINIT
Select if you want to use coreboot implementation of raminit rather than
System Agent/MRC.bin. You should answer Y.
+config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
+ bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
+ default n
+ depends on USE_NATIVE_RAMINIT
+ help
+ Ignore the mainboard's vendor programmed fuses that might limit the
+ maximum DRAM frequency. By selecting this option the fuses will be
+ ignored and the only limits on DRAM frequency are set by RAM's SPD and
+ hard fuses in southbridge's clockgen.
+ Disabled by default as it might causes system instability.
+ Handle with care!
+
config CBFS_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index c6ff551fbf..3e69f4da72 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -402,6 +402,9 @@ unsigned int get_mem_min_tck(void)
/* If this is zero, it just means devicetree.cb didn't set it */
if (!cfg || cfg->max_mem_clock_mhz == 0) {
+ if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES))
+ return TCK_1333MHZ;
+
rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
if ((rev & BASE_REV_MASK) == BASE_REV_SNB) {