cpu/intel/model_206ax: Use tsc monotonic timer

Switch from lapic to tsc.

Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.

Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.

Tested on Lenovo T430.

Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 0 insertions, 124 deletions

diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
index 2f9c43860e..2a4d9bdf9f 100644
--- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc
+++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
@@ -29,7 +29,6 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/walkcbfs.S
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 CPPFLAGS_common += -I$(src)/northbridge/intel/fsp_sandybridge/fsp
diff --git a/src/northbridge/intel/fsp_sandybridge/udelay.c b/src/northbridge/intel/fsp_sandybridge/udelay.c
deleted file mode 100644
index 8f95595c12..0000000000
--- a/src/northbridge/intel/fsp_sandybridge/udelay.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-
-/**
- * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz
- */
-
-void udelay(u32 us)
-{
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-
-	d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
-	multiply_to_tsc(&tscd, us, d);
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
-		tsc1.hi++;
-	}
-	tsc1.lo = dword;
-	tsc1.hi += tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
-}
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index a40fa157ef..846d31bd78 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -43,7 +43,6 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/walkcbfs.S
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 ifneq ($(CONFIG_CHROMEOS),y)
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
deleted file mode 100644
index 7362f75bcc..0000000000
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-
-/**
- * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
- */
-
-void udelay(u32 us)
-{
-	u32 dword;
-	tsc_t tsc, tsc1, tscd;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-
-	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
-	multiply_to_tsc(&tscd, us, d);
-
-	tsc1 = rdtsc();
-	dword = tsc1.lo + tscd.lo;
-	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
-		tsc1.hi++;
-	}
-	tsc1.lo = dword;
-	tsc1.hi += tscd.hi;
-
-	do {
-		tsc = rdtsc();
-	} while ((tsc.hi < tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-}
-
-#if CONFIG_LAPIC_MONOTONIC_TIMER && !defined(__PRE_RAM__)
-#include <timer.h>
-
-void timer_monotonic_get(struct mono_time *mt)
-{
-	tsc_t tsc;
-	msr_t msr;
-	u32 fsb = 100, divisor;
-	u32 d;			/* ticks per us */
-
-	msr = rdmsr(0xce);
-	divisor = (msr.lo >> 8) & 0xff;
-	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
-
-	tsc = rdtsc();
-
-	mt->microseconds = (long)((((uint64_t)tsc.hi << 32) | tsc.lo) / d);
-}
-#endif