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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-20 18:31:38 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-23 08:55:15 +0000
commitce83f3103c9b7d0e6daa6b95544d880660d0b6e9 (patch)
tree2bf02b6492d9f3765c0601d6246b115893f826a7 /src/northbridge/intel
parent3d23890c65e4a0c08bc346e8c3c2b4161440b4c6 (diff)
downloadcoreboot-ce83f3103c9b7d0e6daa6b95544d880660d0b6e9.tar.xz
nb/intel/haswell: Remove variable set but not used
Change-Id: I4e7f74f67f03131fae205a93dae3d61eca9cc0c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32895 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/haswell/raminit.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index c24bb67db7..9beb23cc8e 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -186,7 +186,7 @@ void sdram_initialize(struct pei_data *pei_data)
void setup_sdram_meminfo(struct pei_data *pei_data)
{
- u32 addr_decoder_common, addr_decode_ch[2];
+ u32 addr_decode_ch[2];
struct memory_info* mem_info;
struct dimm_info *dimm;
int ddr_frequency;
@@ -199,7 +199,8 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
die("Failed to add memory info to CBMEM.\n");
memset(mem_info, 0, sizeof(struct memory_info));
- addr_decoder_common = MCHBAR32(0x5000);
+ /* FIXME: Do we need to read MCHBAR32(0x5000) ? */
+ MCHBAR32(0x5000);
addr_decode_ch[0] = MCHBAR32(0x5004);
addr_decode_ch[1] = MCHBAR32(0x5008);