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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-13 16:02:09 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2017-08-20 13:36:29 +0000 |
| commit | 24798a1544a5fa46baca2f7d207fdfbf60517c31 (patch) | |
| tree | 8dcf51325eeeea91a6c9203f99b8f26f2abefe05 /src/northbridge/intel | |
| parent | 6d7a8c1125d17781fe2354eb316df247c82df741 (diff) | |
| download | coreboot-24798a1544a5fa46baca2f7d207fdfbf60517c31.tar.xz | |
nb/intel/x4x: Fix booting with FSB800 DDR667 combination
A small typo in the dll setting code prevented this combination from
booting.
TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2
Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 9c13fc1995..02c7fee475 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -927,7 +927,7 @@ static void dll_ddr2(struct sysinfo *s) if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { - i = MCHBAR8(0x180) & 0xf; + i = MCHBAR8(0x1c8) & 0xf; i = (i + 10) % 14; MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |