diff options
| author | Ronald G. Minnich <rminnich@google.com> | 2013-03-28 17:01:43 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-09 22:16:09 +0200 |
| commit | 2a66d6b804acd22fddc2e51550ba39d2561c1234 (patch) | |
| tree | cc858e8fd6a4c536bff82b7b2cc1e53a12beebe7 /src/northbridge/intel | |
| parent | f42b83e958f4529ef5a859494807914a5601d2f9 (diff) | |
| download | coreboot-2a66d6b804acd22fddc2e51550ba39d2561c1234.tar.xz | |
FOX_WTM2: First pass at FUI.
This lights up the display. We don't get graphics but we are missing the gttsetup
at this point, so that is no shock. The real shock is that anything works at all.
Change-Id: I03fc470334e96878aeb8465044b3cc9c90378735
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3634
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0a67b6a851..dd06867d9c 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -190,20 +190,39 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; - + u32 graphics_base; //, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + + /* the BAR for graphics space is a well known number for + * sandy and ivy. And the resource code renumbers it. + * So it's almost like having two hardcodes. + */ + graphics_base = dev->resource_list[1].base; /* Init graphics power management */ gma_pm_init_pre_vbios(dev); /* PCI Init, will run VBIOS */ +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "Run the VBIOS init\n"); pci_dev_init(dev); +#endif /* Post VBIOS init */ gma_pm_init_post_vbios(dev); +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); + u32 iobase, mmiobase, physbase; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |