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| author | Martin Roth <gaumless@gmail.com> | 2015-04-16 21:20:34 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2015-04-28 20:50:03 +0200 |
| commit | 562d6f30a0745b3da4c61974f8ac1b529dac9d80 (patch) | |
| tree | fed954e864a211d8ecfcdfcadf105f7d2a4a3fac /src/northbridge/intel | |
| parent | ceae968e2cc3d9318c70e34a5424080f9f345eea (diff) | |
| download | coreboot-562d6f30a0745b3da4c61974f8ac1b529dac9d80.tar.xz | |
fsp platforms: consolidate FspNotify calls
Consolidate the FspNotify calls into the FSP driver directory,
using BOOT_STATE_INIT_ENTRY to set up the call times.
Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/9780
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/northbridge.c | 22 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.c | 23 |
2 files changed, 0 insertions, 45 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 14d0853de7..306bb89953 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -112,17 +112,6 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void finalize_dev (device_t dev) -{ - /* - * Notify FSP for PostPciEnumeration. - * Northbridge APIC init should be early and late enough... - */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); -} - static void mc_add_dram_resources(device_t dev) { u32 tomlow, bmbound, bsmmrrl, bsmmrrh; @@ -233,7 +222,6 @@ static struct device_operations pci_domain_ops = { .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, - .final = finalize_dev, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, }; @@ -294,17 +282,7 @@ static void enable_dev(device_t dev) } } -static void finalize_chip(void *chip_info) -{ - /* Notify FSP for ReadyToBoot */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - print_fsp_info(); - FspNotify(EnumInitPhaseReadyToBoot); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); -} - struct chip_operations northbridge_intel_fsp_rangeley_ops = { CHIP_NAME("Intel Rangeley Northbridge") .enable_dev = enable_dev, - .final = finalize_chip, }; diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index fac635df10..17e772329c 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -39,7 +39,6 @@ #include <fsp_util.h> static int bridge_revision_id = -1; -static u8 finished_FSP_after_pci = 0; /* IGD UMA memory */ static uint64_t uma_memory_base = 0; @@ -372,31 +371,9 @@ static void enable_dev(device_t dev) } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } - - /* - * Notify FSP for PostPciEnumeration. - * This call needs to be done before resource allocation. - */ - if (!finished_FSP_after_pci) { - finished_FSP_after_pci = 1; - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); - printk(BIOS_DEBUG, - "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n\n"); - } -} - -static void finalize_chip(void *chip_info) -{ - /* Notify FSP for ReadyToBoot */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - print_fsp_info(); - FspNotify(EnumInitPhaseReadyToBoot); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); } struct chip_operations northbridge_intel_fsp_sandybridge_ops = { CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge") .enable_dev = enable_dev, - .final = finalize_chip, }; |