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authorFurquan Shaikh <furquan@google.com>2020-06-01 13:44:57 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-03 12:22:01 +0000
commit9e94cce35d9e0a22ac169c5e5d4cb7100af730d1 (patch)
treeca02865bf40c67018270a6367663392ae876b6e6 /src/northbridge/intel
parent506479d2a8c1c8f422b5a0257037d563b465dc5d (diff)
downloadcoreboot-9e94cce35d9e0a22ac169c5e5d4cb7100af730d1.tar.xz
northbridge/intel/sandybridge: Update hostbridge.asl to ASL2.0 syntax
This change updates hostbridge.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for google/link. Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/sandybridge/acpi/hostbridge.asl53
1 files changed, 26 insertions, 27 deletions
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index c3561f85b6..c8efc982f9 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -130,17 +130,16 @@ Device (MCHC)
External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
- Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_SB.CP00._PSS), Local1)
+ Local0 = 1 /* Start at P1 */
+ Local1 = SizeOf (\_SB.CP00._PSS)
- While (LLess (Local0, Local1)) {
+ While (Local0 < Local1) {
/* Store _PSS entry Control value to Local2 */
- ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
- If (LEqual (Local2, Arg0)) {
- Return (Subtract (Local0, 1))
+ Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8
+ If (Local2 == Arg0) {
+ Return (Local0 - 1)
}
- Increment (Local0)
+ Local0++
}
Return (0)
@@ -160,23 +159,23 @@ Device (MCHC)
Store ("Set TDP Down", Debug)
/* Set CTC */
- Store (CTCD, CTCS)
+ CTCS = CTCD
/* Set TAR */
- Store (TARD, TARS)
+ TARS = TARD
/* Set PPC limit and notify OS */
- Store (PSSS (TARD), PPCM)
+ PPCM = PSSS (TARD)
PPCN ()
/* Set PL2 to 1.25 * PL1 */
- Divide (Multiply (CTDD, 125), 100, , PL2V)
+ PL2V = (CTDD * 125) / 100
/* Set PL1 */
- Store (CTDD, PL1V)
+ PL1V = CTDD
/* Store the new TDP Down setting */
- Store (CTCD, CTCC)
+ CTCC = CTCD
Release (CTCM)
Return (1)
@@ -196,23 +195,23 @@ Device (MCHC)
Store ("Set TDP Nominal", Debug)
/* Set PL1 */
- Store (CTDN, PL1V)
+ PL1V = CTDN
/* Set PL2 to 1.25 * PL1 */
- Divide (Multiply (CTDN, 125), 100, , PL2V)
+ PL2V = (CTDN * 125) / 100
/* Set PPC limit and notify OS */
- Store (PSSS (TARN), PPCM)
+ PPCM = PSSS (TARN)
PPCN ()
/* Set TAR */
- Store (TARN, TARS)
+ TARS = TARN
/* Set CTC */
- Store (CTCN, CTCS)
+ CTCS = CTCN
/* Store the new TDP Nominal setting */
- Store (CTCN, CTCC)
+ CTCC = CTCN
Release (CTCM)
Return (1)
@@ -343,18 +342,18 @@ Method (_CRS, 0, Serialized)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM
- Store (^MCHC.TLUD, Local0)
- Store (^MCHC.MEBA, Local1)
+ Local0 = ^MCHC.TLUD
+ Local1 = ^MCHC.MEBA
// Check if ME base is equal
- If (LEqual (Local0, Local1)) {
+ If (Local0 == Local1) {
// Use Top Of Memory instead
- Store (^MCHC.TOM, Local0)
+ Local0 = ^MCHC.TOM
}
- Store (Local0, PMIN)
- Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
- Add(Subtract(PMAX, PMIN), 1, PLEN)
+ PMIN = Local0
+ PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
+ PLEN = PMAX - PMIN + 1
Return (MCRS)
}