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authorFurquan Shaikh <furquan@google.com>2020-05-09 17:18:48 -0700
committerFurquan Shaikh <furquan@google.com>2020-05-12 18:59:38 +0000
commitd82c7d24ffc64e7caeaff6ccd7c79d3946142afc (patch)
tree190304f658c214a0ed963df02e95f690d1b485f7 /src/northbridge/intel
parent2f5183c7af57bdefc88999bba62896bbcfe606c6 (diff)
downloadcoreboot-d82c7d24ffc64e7caeaff6ccd7c79d3946142afc.tar.xz
soc/amd/common/block/lpc: Split lpc_set_spibase() into two functions
This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel')
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