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| author | Philipp Deppenwiese <zaolin@das-labor.org> | 2017-10-18 20:26:18 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-01-18 01:45:35 +0000 |
| commit | d88fb36e61beac7b52b6183385de4434895a4995 (patch) | |
| tree | 285f48686df7f318b7b57044991bf70ebd4cd42c /src/northbridge/intel | |
| parent | 64e2d19082636de9e82674ccfca574269bb34712 (diff) | |
| download | coreboot-d88fb36e61beac7b52b6183385de4434895a4995.tar.xz | |
security/tpm: Change TPM naming for different layers.
* Rename tlcl* to tss* as tpm software stack layer.
* Fix inconsistent naming.
Change-Id: I206dd6a32dbd303a6d4d987e424407ebf5c518fa
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 1f31ad611e..4c596539de 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,7 +28,7 @@ #include <device/pci_def.h> #include <device/device.h> #include <halt.h> -#include <security/tpm/tpm.h> +#include <security/tpm/tis.h> #include <northbridge/intel/sandybridge/chip.h> #include "southbridge/intel/bd82x6x/pch.h" #include <southbridge/intel/common/gpio.h> |