diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-04 20:58:55 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-01-06 10:06:21 +0100 |
| commit | e51210dbaeafb91d9eb03eddcd061cfc94a48eab (patch) | |
| tree | 406b3e85908393076dca7ce51b96cc0bfd2c522e /src/northbridge/intel | |
| parent | 00ea28ecf9a9524824c652cd834428bf61fa62e8 (diff) | |
| download | coreboot-e51210dbaeafb91d9eb03eddcd061cfc94a48eab.tar.xz | |
MRC cache: determine flash size on runtime
It should be possible to put coreboot compiled for smaller chip by
putting it at the end of bigger chip. We already have chip size in
flash->size. Use it.
Tested on Lenovo X230.
Change-Id: If8ff03ed72671a9f2745ed4e759a04e83aa7cc37
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/mrccache.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/mrccache.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index f60d0f7993..88dbf7f0c4 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -34,8 +34,8 @@ #endif /* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_ROM_SIZE); +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); } static struct mrc_data_container *next_mrc_block( @@ -212,7 +212,7 @@ static void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -220,7 +220,7 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index e19d2c5a8d..b8120a8c29 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -34,8 +34,8 @@ #endif /* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_ROM_SIZE); +static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { + return ((u32)p + flash->size); } static struct mrc_data_container *next_mrc_block( @@ -212,7 +212,7 @@ static void update_mrc_cache(void *unused) "Need to erase the MRC cache region of %d bytes at %p\n", cache_size, cache_base); - flash->erase(flash, to_flash_offset(cache_base), cache_size); + flash->erase(flash, to_flash_offset(flash, cache_base), cache_size); /* we will start at the beginning again */ cache = cache_base; @@ -220,7 +220,7 @@ static void update_mrc_cache(void *unused) // 4. write mrc data with flash->write() printk(BIOS_DEBUG, "Finally: write MRC cache update to flash at %p\n", cache); - flash->write(flash, to_flash_offset(cache), + flash->write(flash, to_flash_offset(flash, cache), current->mrc_data_size + sizeof(*current), current); } |