diff options
| author | Richard Spiegel <richard.spiegel@silverbackltd.com> | 2017-12-26 08:00:53 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-23 05:45:28 +0000 |
| commit | 254f10e9e60bcfd37b0772c540e99111806cdb3f (patch) | |
| tree | f76797ba9a6cb176d5d9b05c959e5497f041669b /src/northbridge/intel | |
| parent | 843f3abcbdafceff4e698bcf8504172f253f39b7 (diff) | |
| download | coreboot-254f10e9e60bcfd37b0772c540e99111806cdb3f.tar.xz | |
google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO table
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[]
with data from agesa_board_gpios[], wrap format and delete
agesa_board_gpios[] and get_gpio_table(). Then remove the
get_gpio_table() call from BiosCallOuts.c. Finally, remove
get_gpio_table() from
google/kahlee/variants/baseboard/include/baseboard/variants.h.
BUG=b:64140392
TEST=Build grunt. Build and boot kahlee, recording serial output. Search
for "stage bootblock" and "stage ramstage", indicating GPIO being
programmed.
Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions