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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-01 08:54:56 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-07 09:38:06 +0000
commit142b10ee1fa1c68f0c147665ff55b43eb8f0317d (patch)
treeec5f5567802d40e49c7021c625f850d12731b800 /src/northbridge/intel
parentb29da7f79e7cfb16f5d8b23057bd91df760f79d3 (diff)
downloadcoreboot-142b10ee1fa1c68f0c147665ff55b43eb8f0317d.tar.xz
cpu/x86: Fix MSR_PLATFORM_INFO definition
While common to many Intel CPUs, this is not an architectural MSR that should be globally defined for all x86. Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Guckian
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/fsp_rangeley/udelay.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index 01989abb37..08301a37f6 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -18,6 +18,8 @@
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#define MSR_PLATFORM_INFO 0xce
+
/**
* Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
*/