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authorArthur Heymans <arthur@aheymans.xyz>2019-10-03 09:16:10 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-06 10:15:16 +0000
commit3b452e0a797b54a05b97725f4e4e320c51098754 (patch)
tree6cebd0c98dd87522f32a6179051673ae2225e17c /src/northbridge/intel
parentcea4fd9bb059dab2a0c10b48b1c645807665eec2 (diff)
downloadcoreboot-3b452e0a797b54a05b97725f4e4e320c51098754.tar.xz
nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak
This change does the following: - Move PCH init code from the common romstage to sb code, this allows for easier reuse in bootblock - Provide a common minimal LPC io decode setup, mainboards can override this in the mainboard_lpc_init if required - Set up LPC generic IO decode up in romstage based on devicetree settings - Remove the ramstage LPC generic IO decode from ramstage as this is now done in romstage.c - Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as this is already done in the bootblock. Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/nehalem/romstage.c26
1 files changed, 1 insertions, 25 deletions
diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/nehalem/romstage.c
index 83848273a0..c465a99365 100644
--- a/src/northbridge/intel/nehalem/romstage.c
+++ b/src/northbridge/intel/nehalem/romstage.c
@@ -30,8 +30,6 @@
#include <northbridge/intel/nehalem/raminit.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/ibexpeak/me.h>
-#include <southbridge/intel/common/pmclib.h>
-#include <southbridge/intel/common/gpio.h>
/* Platform has no romstage entry point under mainboard directory,
* so this one is named with prefix mainboard.
@@ -47,29 +45,7 @@ void mainboard_romstage_entry(void)
/* TODO, make this configurable */
nehalem_early_initialization(NEHALEM_MOBILE);
- /* mainboard_lpc_init */
- mainboard_lpc_init();
-
- /* Enable GPIOs */
- pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
- pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
- setup_pch_gpios(&mainboard_gpio_map);
-
- /* TODO, make this configurable */
- pch_setup_cir(NEHALEM_MOBILE);
-
- southbridge_configure_default_intmap();
-
- /* Must set BIT0 (hides performance counters PCI device).
- coreboot enables the Rate Matching Hub which makes the UHCI PCI
- devices disappear, so BIT5-12 and BIT28 can be set to hide those. */
- RCBA32(FD) = (1 << 28) | (0xff << 5) | 1;
-
- /* Set reserved bit to 1 */
- RCBA32(FD2) = 1;
-
- early_usb_init(mainboard_usb_ports);
+ early_pch_init();
/* Initialize console device(s) */
console_init();