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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-11 17:12:26 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-09-13 09:58:33 +0000
commit7f50afb0c79fc041a8533586172cae53284d3c9b (patch)
tree2294e2a03069bd25028fe5b9d4fb98367e21df34 /src/northbridge/intel
parent2cce24dd4b9aa106d3ac2e5519fc84a435813c09 (diff)
downloadcoreboot-7f50afb0c79fc041a8533586172cae53284d3c9b.tar.xz
drivers/elog: Add elog_boot_notify()
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/nehalem/early_init.c3
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c3
2 files changed, 2 insertions, 4 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 1f413e3ad1..5bdb5d5e0a 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -139,8 +139,7 @@ void nehalem_early_initialization(int chipset_type)
s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
(((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3);
- if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume)
- boot_count_increment();
+ elog_boot_notify(s3_resume);
/* Device Enable */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN,
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 1b402dcc56..55f2928213 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -74,8 +74,7 @@ void mainboard_romstage_entry(void)
s3resume = southbridge_detect_s3_resume();
- if (CONFIG(ELOG_BOOT_COUNT) && !s3resume)
- boot_count_increment();
+ elog_boot_notify(s3resume);
post_code(0x38);