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| author | Myles Watson <mylesgw@gmail.com> | 2010-03-22 16:33:25 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2010-03-22 16:33:25 +0000 |
| commit | 08e0fb881093c977488de6e8d701dd69369123ec (patch) | |
| tree | 5a7d8aa8415a0b2143ed6f4d52af87191a33561c /src/northbridge/intel | |
| parent | 53b0ea4bf24c0ae51aa9f8447d4ce9d44d46af72 (diff) | |
| download | coreboot-08e0fb881093c977488de6e8d701dd69369123ec.tar.xz | |
Fix all the format string warnings.
Some other random warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/i82810/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i855/northbridge.c | 9 |
3 files changed, 4 insertions, 8 deletions
diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index aff287cb56..d6400d5859 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -56,7 +56,6 @@ static void pcie_init(struct device *dev) static void pcie_bus_enable_resources(struct device *dev) { - u8 val8; if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { printk(BIOS_SPEW, "Enable VGA IO/MEM forwarding on PCIe port\n"); pci_write_config8(dev, PCI_BRIDGE_CONTROL, 8); diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 23e7acffbd..952455a672 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -142,7 +142,7 @@ static void pci_domain_set_resources(device_t dev) drp_value = drp_value >> 4; // >>= 4; //? mess with later tomk += (unsigned long)(translate_i82810_to_mb[drp_value]); - printk(BIOS_DEBUG, "Setting RAM size to %d MB\n", tomk); + printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk); /* Convert tomk from MB to KB. */ tomk = tomk << 10; diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 8587754fc1..03bf3a93b6 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -29,6 +29,7 @@ #include <string.h> #include <bitops.h> #include <cpu/x86/cache.h> +#include <cpu/cpu.h> #include "chip.h" static void ram_resource(device_t dev, unsigned long index, @@ -95,9 +96,7 @@ static void pci_domain_set_resources(device_t dev) * too confusing to get right. Kilobytes are good up to * 4 Terabytes of RAM... */ - uint16_t tolm_r, vga_mem; unsigned long tomk, tolmk; - unsigned long remapbasek, remaplimitk; int idx; /* Get the value of the highest DRB. This tells the end of @@ -120,8 +119,8 @@ static void pci_domain_set_resources(device_t dev) */ /* Report the memory regions */ - printk(BIOS_DEBUG, "tomk = %d\n", tomk); - printk(BIOS_DEBUG, "tolmk = %d\n", tolmk); + printk(BIOS_DEBUG, "tomk = %ld\n", tomk); + printk(BIOS_DEBUG, "tolmk = %ld\n", tolmk); idx = 10; /* avoid pam region */ @@ -165,8 +164,6 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(struct device *dev) { - struct device_path path; - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { dev->ops = &pci_domain_ops; |