summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
diff options
context:
space:
mode:
authorJoseph Smith <joe@settoplinux.org>2010-03-17 03:18:29 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-17 03:18:29 +0000
commit0d7a99669545bef76d57d17fd41ab376e061b109 (patch)
treef0f27f51661d5ead8970d5a65ee7a603549736a6 /src/northbridge/intel
parentbd112980ffcc7d9809dff88b7208e804c54345ab (diff)
downloadcoreboot-0d7a99669545bef76d57d17fd41ab376e061b109.tar.xz
This is kind of a pre CAR patch to properly allocate "shared" graphics memory
area. CONFIG_GFXUMA is used in src/cpu/x86/mtrr/mtrr.c which is called by the cpu. Attached is a revised patch which works well. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> See boot snips below: Root Device assign_resources, bus 0 link: 0 8MB IGD UMA Available memory: 581632KB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 ---------------------------- Adding high table area Adding UMA memory area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 0000000000100000-00000000237effff: RAM 3. 00000000237f0000-00000000237fffff: CONFIGURATION TABLES 4. 0000000023800000-0000000023ffffff: RESERVED git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel')
-rw-r--r--src/northbridge/intel/i82830/northbridge.c24
-rw-r--r--src/northbridge/intel/i82830/raminit.c2
2 files changed, 23 insertions, 3 deletions
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index af9663df09..da76a5d89b 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
+ * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -28,6 +28,8 @@
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
+#include <boot/tables.h>
+#include <arch/coreboot_tables.h>
#include "chip.h"
#include "i82830.h"
@@ -88,6 +90,18 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm;
}
+/* IGD memory */
+uint64_t uma_memory_base=0, uma_memory_size=0;
+
+int add_northbridge_resources(struct lb_memory *mem)
+{
+ printk_debug("Adding IGD UMA memory area\n");
+ lb_add_memory_range(mem, LB_MEM_RESERVED,
+ uma_memory_base, uma_memory_size);
+
+ return 0;
+}
+
#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
@@ -106,8 +120,10 @@ static void pci_domain_set_resources(device_t dev)
if (CONFIG_VIDEO_MB == 512) {
igd_memory = (CONFIG_VIDEO_MB);
+ printk_debug("%dKB IGD UMA\n", igd_memory >> 10);
} else {
igd_memory = (CONFIG_VIDEO_MB * 1024);
+ printk_debug("%dMB IGD UMA\n", igd_memory >> 10);
}
/* Get the value of the highest DRB. This tells the end of
@@ -116,7 +132,11 @@ static void pci_domain_set_resources(device_t dev)
*/
tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
tomk -= igd_memory;
- printk_debug("Memory detected: %ldKB RAM\n", tomk);
+
+ /* For reserving UMA memory in the memory map */
+ uma_memory_base = tomk * 1024ULL;
+ uma_memory_size = igd_memory * 1024ULL;
+ printk_debug("Available memory: %ldKB\n", tomk);
/* Compute the top of low memory. */
tolmk = pci_tolm >> 10;
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index 9e2f3c4bf1..2eea5f0e19 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -48,7 +48,7 @@ Macros and definitions.
* 0x0 for Refresh Disabled (Self Refresh)
* 0x1 for Refresh interval 15.6 us for 133MHz
* 0x2 for Refresh interval 7.8 us for 133MHz
- * 0x7 /* Refresh interval 128 Clocks. (Fast Refresh Mode)
+ * 0x7 for Refresh interval 128 Clocks. (Fast Refresh Mode)
*/
#define RAM_COMMAND_REFRESH 0x1