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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 15:06:17 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-04-13 14:49:31 +0000 |
| commit | 425e75a2db999d65400b49ebe65ae26c64aabcd9 (patch) | |
| tree | b2407f1d50cc8a6129f226d7df919afcd2fd89f7 /src/northbridge/intel | |
| parent | a3caa2d3bbe791c39af2b56ae6f94ec83c4e09e2 (diff) | |
| download | coreboot-425e75a2db999d65400b49ebe65ae26c64aabcd9.tar.xz | |
sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.
Tested on Thinkpad X60.
Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/pineview/romstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index e6a344e738..771434472e 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -26,6 +26,7 @@ #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> |