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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-05-24 18:42:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-06 09:40:38 +0000 |
| commit | abf51abe1d30386cc6e4aee8aca0cd2fd225f853 (patch) | |
| tree | e657e0fc21a47b81bcc2481b63827137fc478a72 /src/northbridge/intel | |
| parent | e1df7eef91c4f2e7b87a02d0cff837c8805e4bbb (diff) | |
| download | coreboot-abf51abe1d30386cc6e4aee8aca0cd2fd225f853.tar.xz | |
src: Remove unused '#include <cpu/x86/smm.h>'
Change-Id: I1632d03a7a73de3e3d3a83bf447480b0513873e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41685
Reviewed-by: David Guckian
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index a728e0e8cf..c282aea044 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -11,7 +11,6 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <cpu/x86/smm.h> #include <boot/tables.h> #include "chip.h" |