diff options
| author | Alexander Couzens <lynxis@fe80.eu> | 2015-02-26 01:30:40 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-13 14:51:42 +0100 |
| commit | b7b83719bf6a304240e221fd5f801debc400461b (patch) | |
| tree | 5513f53ff23faf8fe04315ce8b2db4d53ff5e343 /src/northbridge/intel | |
| parent | ed48dfdc4edd08d4e9641a87839a9904fdd98c13 (diff) | |
| download | coreboot-b7b83719bf6a304240e221fd5f801debc400461b.tar.xz | |
northbridge/intel/nehalem: don't set FERR_CAPABILITY on BSP
This capability means:
FERR messages are sent out on system detected an
unmasked floating point x87 FPU error.
Even though this capability is supported on nehalem it doesn't
make sense to set it in early stage. This MSR
has a core scope which results in an unsync MSR because
it's not set on other cores than the BSP.
Found-by: BITS
Tested-on: lenovo thinkpad x201t
Change-Id: Ief3c04f57ac69e7289fbd37dbc3fd239f9098155
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/nehalem/early_init.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 56c0d68724..9c9d1b4512 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -131,11 +131,6 @@ static void early_cpu_init (void) m = rdmsr(MSR_IA32_MISC_ENABLES); m.lo |= 0x10000; wrmsr(MSR_IA32_MISC_ENABLES, m); - - m = rdmsr(0x1f1); - m.lo |= 1; - wrmsr(0x1f1, m); - } void nehalem_early_initialization(int chipset_type) |