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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-06-10 13:47:56 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-06-15 16:31:01 +0000 |
| commit | d844431af09aafd65656f77b699c737966b30086 (patch) | |
| tree | 85994ff365a99ff56d38adfab1a8295173083cec /src/northbridge/intel | |
| parent | e94335e9fd00ee5c707eb927922ef09b9487c5d6 (diff) | |
| download | coreboot-d844431af09aafd65656f77b699c737966b30086.tar.xz | |
vendorcode/agesa: Fix check for valid PhyLane
Found using GCC with flag -Wlogical-op
Change-Id: Ia04ac5b1d0a4434c0ab2ca583b9b03dbfd0ffd41
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33362
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel')
0 files changed, 0 insertions, 0 deletions