src: capitalize 'RAM'

Change-Id: Ia05cb2de1b9f2a36fc9ecc22fb82f0c14da00a76
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

6 files changed, 11 insertions, 11 deletions

diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index d34820eb3d..33abc510a1 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -133,8 +133,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 {
 	uintptr_t top_of_ram;
 
-	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
-	 * ram to cover both cbmem as the TSEG region.
+	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+	 * RAM to cover both cbmem as the TSEG region.
 	 */
 	top_of_ram = (uintptr_t)cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 54141205ec..83157d88ac 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -99,8 +99,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 {
 	uintptr_t top_of_ram;
 
-	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
-	 * ram to cover both cbmem as the TSEG region.
+	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+	 * RAM to cover both cbmem as the TSEG region.
 	 */
 	top_of_ram = (uintptr_t)cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 0aa70cdb34..9fde9f7fdb 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -149,8 +149,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 {
 	uintptr_t top_of_ram;
 
-	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
-	 * ram to cover both cbmem as the TSEG region.
+	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+	 * RAM to cover both cbmem as the TSEG region.
 	 */
 	top_of_ram = (uintptr_t)cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 6ebd7e0bb6..0784c11313 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -58,12 +58,12 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 
 	top_of_ram = (uintptr_t)cbmem_top();
 	/* Cache 8MiB below the top of ram. On sandybridge systems the top of
-	 * ram under 4GiB is the start of the TSEG region. It is required to
+	 * RAM under 4GiB is the start of the TSEG region. It is required to
 	 * be 8MiB aligned. Set this area as cacheable so it can be used later
 	 * for ramstage before setting up the entire RAM as cacheable. */
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
 
-	/* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
+	/* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems
 	 * is where the TSEG region resides. However, it is not restricted
 	 * to SMM mode until SMM has been relocated. By setting the region
 	 * to cacheable it provides faster access when relocating the SMM
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 1924ddf678..334e6c7a37 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -144,8 +144,8 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 {
 	uintptr_t top_of_ram;
 
-	/* Cache 8 MiB region below the top of ram and 2 MiB above top of
-	 * ram to cover both cbmem as the TSEG region.
+	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
+	 * RAM to cover both cbmem as the TSEG region.
 	 */
 	top_of_ram = (uintptr_t)cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index dd48d8ab63..1e871c7600 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -1636,7 +1636,7 @@ static void set_dradrb(struct sysinfo *s)
 		dual_channel_size = MIN(size_ch0, size_ch1) * 2;
 	} else {
 		if (size_ch0 == 0) {
-			/* ME needs ram on CH0 */
+			/* ME needs RAM on CH0 */
 			size_me = 0;
 			/* TOTEST: bailout? */
 		} else {