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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-22 12:55:32 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-26 10:19:56 +0000 |
| commit | 098240eb4fd4ef59510d5138538f2a2f7cc5dcdc (patch) | |
| tree | 6dd499bfe9d74040689b034478b1b96e377ea4f8 /src/northbridge/intel | |
| parent | 0c3936e41b16f11abda5b0f78d5d38caa9f179e3 (diff) | |
| download | coreboot-098240eb4fd4ef59510d5138538f2a2f7cc5dcdc.tar.xz | |
nb/intel/sandybridge: Use IOSAV_BYTE_SERROR_C_ch macro
This changes the binary because the operations get reordered, but it is
otherwise equivalent.
Change-Id: I362187b2889e6f7a68bf752a23c1279cebf961f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index a8480a7661..d10b859575 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2626,7 +2626,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } /* FIXME: This register only exists on Ivy Bridge */ - raw_stats[edge] = MCHBAR32(0x436c + channel * 0x400); + raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { @@ -2797,8 +2797,8 @@ int discover_timC_write(ramctr_timing *ctrl) test_timC_write (ctrl, channel, slotrank); /* FIXME: Another IVB-only register! */ - raw_stats[timC] = - MCHBAR32(0x436c + channel * 0x400); + raw_stats[timC] = MCHBAR32( + IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { struct run rn; |