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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-19 20:38:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-22 11:03:42 +0200 |
| commit | 65cc526f6f47755b4492cd9fc2134fb2dd067e90 (patch) | |
| tree | 9b7357287b96f73a762592ccc8b7d2153eff1d46 /src/northbridge/intel | |
| parent | c5400efc11e181caf0babaa6001de18e3f23c6af (diff) | |
| download | coreboot-65cc526f6f47755b4492cd9fc2134fb2dd067e90.tar.xz | |
Ignore RAMTOP for MTRRs
Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.
With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.
Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index 53bf17c8d2..b69efbc4bb 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -928,9 +928,9 @@ static void set_receive_enable(const struct mem_controller *ctrl) static void cache_ramstage(void) { - /* Enable caching for lower 1MB and ram stage using variable mtrr */ + /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ disable_cache(); - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); + set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); } |