sizeram removal/conversion.

- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 129 insertions, 101 deletions

diff --git a/src/northbridge/transmeta/tm5800/northbridge.c b/src/northbridge/transmeta/tm5800/northbridge.c
index d3576a9143..107ebe2aed 100644
--- a/src/northbridge/transmeta/tm5800/northbridge.c
+++ b/src/northbridge/transmeta/tm5800/northbridge.c
@@ -1,8 +1,6 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
-#include <mem.h>
-#include <part/sizeram.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -13,111 +11,141 @@
 #include "chip.h"
 #include "northbridge.h"
 
-struct mem_range *sizeram(void)
+#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
+
+static void pci_domain_read_resources(device_t dev)
 {
-	unsigned long mmio_basek;
-	static struct mem_range mem[10];
-	device_t dev;
-	int i, idx;
-
-#warning "FIXME handle interleaved nodes"
-	dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-	if (!dev) {
-		printk_err("Cannot find PCI: 0:18.1\n");
-		return 0;
-	}
-	mmio_basek = (dev_root.resource[1].base >> 10);
-	/* Round mmio_basek to something the processor can support */
-	mmio_basek &= ~((1 << 6) -1);
-
-#if 1
-#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
-	/* Round the mmio hold to 256M */
-	mmio_basek &= ~((256*1024) - 1);
-#endif
-
-#if 0
-	printk_debug("mmio_base: %dKB\n", mmio_basek);
-#endif
-
-	for (idx = i = 0; i < 8; i++) {
-		uint32_t base, limit;
-		unsigned basek, limitk, sizek;
-		base  = pci_read_config32(dev, 0x40 + (i<<3));
-		limit = pci_read_config32(dev, 0x44 + (i<<3));
-		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
-			continue;
-		}
-		basek = (base & 0xffff0000) >> 2;
-		limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
-		sizek = limitk - basek;
-		if ((idx > 0) &&
-		    ((mem[idx - 1].basek + mem[idx - 1].sizek) == basek)) {
-			mem[idx -1].sizek += sizek;
-		} else {
-			mem[idx].basek = basek;
-			mem[idx].sizek = sizek;
-			idx++;
-		}
-	
-		/* see if we need a hole from 0xa0000 to 0xbffff */
-		if ((mem[idx-1].basek < ((8*64)+(8*16))) /* 640 */ && 
-		    (mem[idx-1].sizek > ((8*64)+(16*16))) /* 768 */ ) {
-#warning "FIXME: this left 0xA0000 to 0xBFFFF undefined"
-			mem[idx].basek = (8*64)+(16*16);
-			mem[idx].sizek = mem[idx-1].sizek - ((8*64)+(16*16));
-			mem[idx-1].sizek = ((8*64)+(8*16)) - mem[idx-1].basek;
-			idx++;
-		}	
-		
-		/* See if I need to split the region to accomodate pci memory space */
-		if ((mem[idx - 1].basek <= mmio_basek) &&
-		    ((mem[idx - 1].basek + mem[idx - 1].sizek) >  mmio_basek)) {
-			if (mem[idx - 1].basek < mmio_basek) {
-				unsigned pre_sizek;
-				pre_sizek = mmio_basek - mem[idx - 1].basek;
-				mem[idx].basek = mmio_basek;
-				mem[idx].sizek = mem[idx - 1].sizek - pre_sizek;
-				mem[idx - 1].sizek = pre_sizek;
-				idx++;
-			}
-			if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
-				idx -= 1;
-			} else {
-				mem[idx - 1].basek = 4*1024*1024;
-				mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
-			}
+        struct resource *resource;
+        unsigned reg;
+
+        /* Initialize the system wide io space constraints */
+        resource = new_resource(dev, 0);
+        resource->base  = 0x400;
+        resource->limit = 0xffffUL;
+        resource->flags = IORESOURCE_IO;
+        compute_allocate_resource(&dev->link[0], resource,
+                IORESOURCE_IO, IORESOURCE_IO);
+
+        /* Initialize the system wide memory resources constraints */
+        resource = new_resource(dev, 1);
+        resource->limit = 0xffffffffULL;
+        resource->flags = IORESOURCE_MEM;
+        compute_allocate_resource(&dev->link[0], resource,
+                IORESOURCE_MEM, IORESOURCE_MEM);
+}
+
+static void ram_resource(device_t dev, unsigned long index,
+        unsigned long basek, unsigned long sizek)
+{
+        struct resource *resource;
+
+        if (!sizek) {
+                return;
+        }
+        resource = new_resource(dev, index);
+        resource->base  = ((resource_t)basek) << 10;
+        resource->size  = ((resource_t)sizek) << 10;
+        resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
+                IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
+
+static void pci_domain_set_resources(device_t dev)
+{
+        struct resource *resource, *last;
+	device_t mc_dev;
+        uint32_t pci_tolm;
+
+        pci_tolm = 0xffffffffUL;
+        last = &dev->resource[dev->resources];
+        for(resource = &dev->resource[0]; resource < last; resource++)
+        {
+                compute_allocate_resource(&dev->link[0], resource,
+                        BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
+
+                resource->flags |= IORESOURCE_STORED;
+                report_resource_stored(dev, resource, "");
+
+                if ((resource->flags & IORESOURCE_MEM) &&
+                        (pci_tolm > resource->base))
+                {
+                        pci_tolm = resource->base;
+                }
+        }
+
+	mc_dev = dev->link[0].children;
+	if (mc_dev) {
+		/* Figure out which areas are/should be occupied by RAM.
+		 * This is all computed in kilobytes and converted to/from
+		 * the memory controller right at the edges.
+		 * Having different variables in different units is
+		 * too confusing to get right.  Kilobytes are good up to
+		 * 4 Terabytes of RAM...
+		 */
+		unsigned long tomk, tolmk;
+		int idx;
+
+#warning "This is hardcoded to 1MiB of RAM for now"
+		tomk = 1024;
+		/* Compute the top of Low memory */
+		tolmk = pci_tolm >> 10;
+		if (tolmk >= tomk) {
+			/* The PCI hole does does not overlap the memory.
+			 */
+			tolmk = tomk;
 		}
+		/* Report the memory regions */
+		idx = 10;
+		ram_resource(dev, idx++, 0, 640);
+		ram_resource(dev, idx++, 768, tolmk - 768);
 	}
-#if 1
-	for (i = 0; i < idx; i++) {
-		printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
-			     i, mem[i].basek, i, mem[i].sizek);
-	}
-#endif
-	while (idx < sizeof(mem)/sizeof(mem[0])) {
-		mem[idx].basek = 0;
-		mem[idx].sizek = 0;
-		idx++;
-	}
-	return mem;
+	assign_resources(&dev->link[0]);
 }
 
-static struct device_operations northbridge_operations = {
-	.read_resources   = tm5800_read_resources,
-	.set_resources    = tm5800_set_resources,
-	.enable_resources = tm5800_enable_resources,
-	.init             = mcf0_control_init,
-	.scan_bus         = tm5800_scan_chains,
-	.enable           = 0,
-};
+static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
+{
+        max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
+        return max;
+}
+
+static struct device_operations pci_domain_ops = {
+        .read_resources   = pci_domain_read_resources,
+        .set_resources    = pci_domain_set_resources,
+        .enable_resources = enable_childrens_resources,
+        .init             = 0,
+        .scan_bus         = pci_domain_scan_bus,
+};  
 
-static struct pci_driver mcf0_driver __pci_driver = {
-	.ops    = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = 0x1100,
+static void cpu_bus_init(device_t dev)
+{
+        initialize_cpus(&dev->link[0]);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+        .read_resources   = cpu_bus_noop,
+        .set_resources    = cpu_bus_noop,
+        .enable_resources = cpu_bus_noop,
+        .init             = cpu_bus_init,
+        .scan_bus         = 0,
 };
 
-struct chip_operations northbridge_amd_tm5800_control = {
-	.name   = "Transmeta tm5800 Northbridge",
+static void enable_dev(struct device *dev)
+{
+        struct device_path path;
+
+        /* Set the operations if it is a special bus type */
+        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+                dev->ops = &pci_domain_ops;
+        }
+        else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+                dev->ops = &cpu_bus_ops;
+        }
+}
+
+struct chip_operations northbridge_transmeta_tm5800_control = {
+	.name       = "Transmeta tm5800 Northbridge",
+	.enable_dev = enable_dev, 
 };