diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
| commit | 57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch) | |
| tree | 3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/northbridge/via/vx800 | |
| parent | 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff) | |
| download | coreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz | |
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/via/vx800')
| -rw-r--r-- | src/northbridge/via/vx800/examples/romstage.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index 5f9dc52e67..f0e535a02c 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -38,13 +38,10 @@ #include "lib/delay.c" #include "lib/memcpy.c" #include "cpu/x86/lapic/boot_cpu.c" - #include "driving_clk_phase_data.c" - #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" - static int acpi_is_wakeup_early_via_vx800(void) { device_t dev; @@ -77,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } - static void enable_mainboard_devices(void) { device_t dev; @@ -103,10 +99,8 @@ static void enable_shadow_ram(void) /* 0xe0000-0xeffff - elfload? */ pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); - } - /* this table contains the value needed to be set before begin to init dram. Note: REV_Bx should be cared when porting a new board!!!!! */ @@ -182,7 +176,8 @@ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { #define gCom1Base 0x3f8 #define gCom2Base 0x2f8 -void EmbedComInit() + +void EmbedComInit(void) { u8 ByteVal; u16 ComBase; @@ -233,8 +228,6 @@ void EmbedComInit() ByteVal = (ByteVal & 0x3F) | 0xC0; pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); - - //enable embeded com1 and com2 D17F0RxB0[5,4] ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); ByteVal = ByteVal & 0xcf; @@ -296,8 +289,6 @@ void EmbedComInit() //while(1); } -/* cache_as_ram.inc jump to here -*/ void main(unsigned long bist) { unsigned cpu_reset = 0; @@ -311,7 +302,6 @@ void main(unsigned long bist) //enable_vx800_serial(); //uart_init(); - /* 1. D15F0 a) RxBAh = 71h |