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| author | Martin Roth <martinroth@google.com> | 2016-07-29 14:07:30 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-08-01 21:44:45 +0200 |
| commit | 0cd338e6e489eacfedb8fab3ff161b1578d08f07 (patch) | |
| tree | 8b729260de5a406dc22869ff5c5236ba77fbb0ed /src/northbridge/via/vx900/early_host_bus_ctl.c | |
| parent | bb9722bd775d575401edff14a9b80406ecbd974a (diff) | |
| download | coreboot-0cd338e6e489eacfedb8fab3ff161b1578d08f07.tar.xz | |
Remove non-ascii & unprintable characters
These non-ascii & unprintable characters aren't needed.
Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/via/vx900/early_host_bus_ctl.c')
| -rw-r--r-- | src/northbridge/via/vx900/early_host_bus_ctl.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/via/vx900/early_host_bus_ctl.c b/src/northbridge/via/vx900/early_host_bus_ctl.c index 64680c5e28..159b2a4273 100644 --- a/src/northbridge/via/vx900/early_host_bus_ctl.c +++ b/src/northbridge/via/vx900/early_host_bus_ctl.c @@ -20,9 +20,9 @@ static void vx900_cpu_bus_preram_setup(void) { /* Faster CPU to DRAM Cycle */ pci_mod_config8(HOST_BUS, 0x50, 0x0f, 0x08); - /* CPU Interface Control – Basic Options */ + /* CPU Interface Control - Basic Options */ pci_mod_config8(HOST_BUS, 0x51, 0, 0x6c); - /*CPU Interface Control – Advanced Options */ + /*CPU Interface Control - Advanced Options */ pci_write_config8(HOST_BUS, 0x52, 0xc7); /* Enable 8QW burst and 4QW request merging [4] and [2] * and special mode for read cycles bit[3] */ |