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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-09 18:55:58 +0200
committerMartin Roth <martinroth@google.com>2018-08-10 21:25:53 +0000
commit3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch)
tree7b5096ca1f81fecf70418020aba184e446f995e0 /src/northbridge/via/vx900
parent1895838e7a3807a6fce324f0dfed193a3821f6df (diff)
downloadcoreboot-3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d.tar.xz
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/via/vx900')
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index eec4aa357f..17a87bbe97 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -42,7 +42,7 @@
*
* The capture window is not calibrated, but preset. Whether that preset is
* universal or frequency dependent, and whether it is board-specific or not is
- * not yet clear. @see vx900_dram_calibrate_recieve_delays().
+ * not yet clear. @see vx900_dram_calibrate_receive_delays().
*
* 4GBit and 8GBit modules may not work. This is untested. Modules with 11
* column address bits are not tested. @see vx900_dram_map_row_col_bank()
@@ -166,7 +166,7 @@ static pci_reg8 mcu_init_config[] = {
{0x66, 0x80}, /* DRAM Queue / Arbitration */
{0x69, 0xc6}, /* Bank Control: 8 banks, high priority refresh */
{0x6a, 0xfc}, /* DRAMC Request Reorder Control */
- {0x6e, 0x38}, /* Burst lenght: 8, burst-chop: enable */
+ {0x6e, 0x38}, /* Burst length: 8, burst-chop: enable */
{0x73, 0x04}, /* Close All Pages Threshold */
/* The following need to be dynamically asserted */
@@ -1224,7 +1224,7 @@ static void vx900_rxdqs_adjust(delay_range * dly)
vx900_write_0x78_0x7f(dly->avg);
}
-static void vx900_dram_calibrate_recieve_delays(vx900_delay_calib * delays,
+static void vx900_dram_calibrate_receive_delays(vx900_delay_calib * delays,
u8 pinswap)
{
size_t n_tries = 0;
@@ -1417,7 +1417,7 @@ static void vx900_dram_calibrate_delays(const ramctr_timing * ctrl,
/* Only run on first rank, remember? */
break;
}
- vx900_dram_calibrate_recieve_delays(&delay_cal,
+ vx900_dram_calibrate_receive_delays(&delay_cal,
ranks->flags[i].pins_mirrored);
printram("RX DQS calibration results\n");
dump_delay_range(delay_cal.rx_dqs);