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authorPatrick Rudolph <siro@das-labor.org>2017-01-31 19:43:17 +0100
committerMartin Roth <martinroth@google.com>2017-03-10 11:17:27 +0100
commit6e53ae6f5c12b70c2a86370f0dd9df37a12c8118 (patch)
treec647451229c70fe79a50bdba06f5359d9413d093 /src/northbridge/via/vx900
parent7e4d12c5b12107bb7682e050c66f97000e064ce2 (diff)
downloadcoreboot-6e53ae6f5c12b70c2a86370f0dd9df37a12c8118.tar.xz
device/dram/ddr2: Add common ddr2 spd decoder
Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid compilation errors. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18273 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/via/vx900')
-rw-r--r--src/northbridge/via/vx900/raminit_ddr3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index 4878571742..2de7734c17 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -703,7 +703,7 @@ static void vx900_dram_freq(ramctr_timing * ctrl)
pci_mod_config8(MCU, 0x6b, 0x80, 0x00);
/* Step 8 - If we have registered DIMMs, we need to set bit[0] */
- if (dimm_is_registered(ctrl->dimm_type)) {
+ if (spd_dimm_is_registered_ddr3(ctrl->dimm_type)) {
printram("Enabling RDIMM support in memory controller\n");
pci_mod_config8(MCU, 0x6c, 0x00, 0x01);
}