diff options
author | Martin Roth <gaumless@gmail.com> | 2015-01-06 10:20:42 -0700 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2015-01-08 21:59:42 +0100 |
commit | 543888d5820ce28cbf1e03d53da9e7f75001c4c7 (patch) | |
tree | 354521342a7c048b85025cbc329a3b6d618eeeeb /src/northbridge/via/vx900 | |
parent | d7689e4ad588ee1affee1d4edb3e5b0bd8098b0a (diff) | |
download | coreboot-543888d5820ce28cbf1e03d53da9e7f75001c4c7.tar.xz |
northbridg/via/vx900: Doxygen fixes
- @todo has to be lowercase for doxygen
- Fix some parameters that had changed in the code.
- The @file entries needed to be more specific.
Change-Id: Icdce08735f581609cd25cce41e986c71435368a4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8154
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/northbridge/via/vx900')
-rw-r--r-- | src/northbridge/via/vx900/chrome9hd.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx900/early_smbus.c | 3 | ||||
-rw-r--r-- | src/northbridge/via/vx900/lpc.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx900/northbridge.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx900/pcie.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx900/sata.c | 2 | ||||
-rw-r--r-- | src/northbridge/via/vx900/traf_ctrl.c | 2 |
7 files changed, 8 insertions, 7 deletions
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 78a1a88a19..9e506dc4d4 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -53,7 +53,7 @@ * the IGP is able to use it. GRUB2 and linux are capable of getting a usable * text console, which uses the monitor's native resolution (even 1920x1080). * The graphical console (linux) does not work properly. - * @TODO + * @todo * 1. Figure out what sequence we need to do to get the VGA BIOS running * properly. Use the code provided by VIA and compare their sequence to ours, * fill in any missing steps, etc. diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c index e796d8d418..14dd9ec8a7 100644 --- a/src/northbridge/via/vx900/early_smbus.c +++ b/src/northbridge/via/vx900/early_smbus.c @@ -48,7 +48,8 @@ static void smbus_delays(int delays) /** * Read a byte from the SMBus. * - * @param dimm The address location of the DIMM on the SMBus. + * @param smbus_dev The PCI address of the SMBus device . + * @param addr The address location of the DIMM on the SMBus. * @param offset The offset the data is located at. */ u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index bb2f1b2745..3cff6b0bf6 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -30,7 +30,7 @@ #include "chip.h" /** - * @file lpc.c + * @file vx900/lpc.c * * STATUS: * We do a fair bit of setup, and most of it seems to work fairly well. There diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index e1f744c280..5e564a19c1 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -36,7 +36,7 @@ static uint64_t uma_memory_base = 0; static uint64_t uma_memory_size = 0; /** - * @file northbridge.c + * @file vx900/northbridge.c * * STATUS: Pretty good * One thing that needs to be thoroughly tested is the remap above 4G logic. diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c index b748c392d1..ef9f636d31 100644 --- a/src/northbridge/via/vx900/pcie.c +++ b/src/northbridge/via/vx900/pcie.c @@ -26,7 +26,7 @@ #include "vx900.h" /** - * @file pcie.c + * @file vx900/pcie.c * * STATUS: * We do part of the sequence to initialize the PCIE link. The problem is that diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c index c5f36a8fdd..169f383017 100644 --- a/src/northbridge/via/vx900/sata.c +++ b/src/northbridge/via/vx900/sata.c @@ -24,7 +24,7 @@ #include "vx900.h" /** - * @file sata.c + * @file vx900/sata.c * * STATUS: Pretty good * The only issue is the SATA EPHY configuration. We do not know if it is board diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 2e73ea439e..5183391c76 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -28,7 +28,7 @@ #include "chip.h" /** - * @file traf_ctrl.c + * @file vx900/traf_ctrl.c * * STATUS: * The same issues with the IOAPIC pointe in lpc.c also apply here. |