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authorElyes HAOUAS <ehaouas@noos.fr>2019-04-05 18:11:19 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-04-23 10:01:21 +0000
commit351e3e520ba71b4aafaf930af37f78b71c1d7251 (patch)
treeeb872d8fb0aaefad7b313e9dd5e31fe1e7cf3242 /src/northbridge/via
parent20eaef024cb06677de10d018e6f70c28d1841290 (diff)
downloadcoreboot-351e3e520ba71b4aafaf930af37f78b71c1d7251.tar.xz
src: Use include <console/console.h> when appropriate
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
Diffstat (limited to 'src/northbridge/via')
-rw-r--r--src/northbridge/via/vx900/vx900.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h
index 9e30638892..96d821ac4d 100644
--- a/src/northbridge/via/vx900/vx900.h
+++ b/src/northbridge/via/vx900/vx900.h
@@ -28,7 +28,6 @@
#include <device/pci_ops.h>
#include <device/pci.h>
-#include <console/console.h>
u32 vx900_get_tolm(void);
void vx900_set_chrome9hd_fb_size(u32 size_mb);